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Material Choices for Tunnel Dielectric Layer and Gate Blocking Layer for Ferroelectric NAND Applications

Lance Fernandes,Prasanna Venkatesan Ravindran,Taeyoung Song,Dipjyoti Das,Chinsung Park,Nashrah Afroze,Mengkun Tian,Hang Chen,Winston Chern,Kijoon Kim,Jongho Woo,Suhwan Lim,Kwangsoo Kim,Wanki Kim,Daewon Ha,Shimeng Yu,Suman Datta,Asif Khan

IEEE ELECTRON DEVICE LETTERS（2024）

Cited 3|Views3
Key words
Logic gates,Dielectrics,Dielectric materials,Threshold voltage,Performance evaluation,Iron,FeFETs,Ferroelectric,vertical NAND,memory window,ISPP
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