Strategies for a Wide Memory Window of Ferroelectric FET for Multilevel Ferroelectric VNAND Operation
IEEE ELECTRON DEVICE LETTERS（2024）
Key words
Logic gates,Insulators,FeFETs,Voltage,Silicon compounds,Silicon,Iron,Vertical NAND,ferroelectrics,FeFET,gate stack,polarization,trapped charge,band engineering,FN tunneling,ISPP slope
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