13.10 A 4nm 48gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets
IEEE International Solid-State Circuits Conference（2024）
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Deep Learning,Small Area,Industrial Development,Power Consumption,Pulse Width,Abnormal Behavior,Training Strategy,High-performance Computing,Dynamic Stress,Standard Software,Eyes Open,Settling Time,Advanced Software,Capacitive Coupling,Advanced Driver Assistance Systems,High-speed Operation,Calibration Algorithm,Calibration Strategy,Inter-symbol Interference,Eye Diagrams
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