Byoung-Joo Yoo - Department of Advanced Material Science and;Engineering;Kangwon National University

基本信息

Career Trajectory

Bio

Byoung-Joo Yoo (Member, IEEE) received the B.S. degree in electrical engineering from Korea University, Seoul, South Korea, in 2005, and the M.S. and Ph.D. degrees in electrical engineering from Seoul National University, Seoul, in 2007 and 2013, respectively. He is currently a Principle Engineer with Samsung Electronics, Hwaseong, South Korea. His current research focuses on the high-speed serializer–deserializer (SerDes) architecture for next-generation wireline links. His expertise mainly includes digital and analog integrated circuit design for die-to-die interfaces and giga-bit Ethernet protocols.

Research Interests

Papers共 17 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

13.10 A 4nm 48gb/s/wire Single-Ended NRZ Parallel Transceiver with Offset-Calibration and Equalization Schemes for Next-Generation Memory Interfaces and Chiplets

Kihwan Seong,Wooseuk Oh, Hyunwoo Lee,Gyeom-Je Bae,Youngseob Suh,Hyemun Lee, Juyoung Kim,Eunsu Kim, Yeongeon Kang, Gunhu Mo, Youjin Lee, Mingyeong Kim, Seongno Lee, Donguk Park,Byoung-Joo Yoo,Hyo-Gyuem Rhew,Jongshin Shin

IEEE International Solid-State Circuits Conference（2024）

Cited1Views0EIWOSBibtex

A 4nm 32gb/s 8tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver with Equalization Schemes and Training Techniques

Kihwan Seong,Donguk Park,Gyeomje Bae,Hyunwoo Lee,Youngseob Suh,Wooseuk Oh,Hyemun Lee, Ju‐Young Kim,Takgun Lee,Geonhoo Mo,Sukhyun Jung,Dongcheol Choi,Byoung-Joo Yoo,Sanghune Park,Hyo-Gyuem Rhew,Jongshin Shin

openalex（2023）

Cited0Views0Bibtex

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques

Kihwan Seong,Donguk Park,Gyeom-Je Bae,Hyunwoo Lee,Youngseob Suh,Wooseuk Oh,Hyemun Lee,Juyoung Kim,Takgun Lee,Geonhoo Mo,Sukhyun Jung,Dongcheol Choi,Byoung-Joo Yoo,Sanghune Park,Hyo-Gyuem Rhew,Jongshin Shin

ISSCCpp.114-115, (2023)

Cited20Views0EIWOSBibtex

A Design of an Area-Efficient 10-Ghz Phase-Locked Loop for Source-Synchronous, Multi-Channel Links in 90-Nm CMOS Technology

Woorham Bae,Deog-Kyoon Jeong,Byoung-Joo Yoo

PROCEEDINGS OF THE 2014 IEEE 17TH INTERNATIONAL SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CI...（2014）

Cited1Views0EIWOSBibtex

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

Byoung-Joo Yoo,Woo-Rham Bae,Jiho Han,Jaeha Kim,Deog-Kyoon Jeong

IEEE Transactions on Very Large Scale Integration (VLSI) Systems（2013）

Cited6Views0EIWOSBibtex

A Model-First Design and Verification Flow for Analog-Digital Convergence Systems: A High-Speed Receiver Example in Digital TVs

Jaeha Kim,Sigang Ryu,Byoungjoo Yoo,Hanseok Kim,Yunju Choi,Deog-Kyoon Jeong

2012 IEEE International Symposium on Circuits and Systems（2012）

Cited4Views0EIWOSBibtex

Author Statistics

Co-Author

Co-Institution

D-Core

合作者
学生
导师

No result temporarily, you can search similar Scholar with the same research interest

Data Disclaimer

The page data are from open Internet sources, cooperative publishers and automatic analysis results through AI technology. We do not make any commitments and guarantees for the validity, accuracy, correctness, reliability, completeness and timeliness of the page data. If you have any questions, please contact us by email: report@aminer.cn