ASIC Accelerator in 28 Nm for the Post-Quantum Digital Signature Scheme XMSS
2020 IEEE 38th International Conference on Computer Design (ICCD)（2020）
Key words
ASIC implementation,post-quantum digital signature scheme XMSS,pipelined XMSS Leaf accelerator,XMSS algorithm,ASIC designs,Artix-7 FPGA,accelerator architectures,post-quantum cryptographic accelerators,ASIC accelerator,nonpipelined accelerator,size 28.0 nm
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