Circuit and Physical Design Implementation of the Microprocessor Chip for the Zenterprise System

James Warnock,Yiu-Hing Chan,Sean Carey,Huajun Wen, Pat Meaney,Guenter Gerwig,Howard H. Smith,Yuen Chan,John Davis,Paul Bunce,Antonio Pelella, Dan Rodko,Pradip Patel,Thomas Strach,Doug Malone,Frank Malgioglio,Jose Neves,David L. Rude,William Huott

IEEE Journal of Solid-State Circuits（2012）

Cited 57|Views107

Key words

Cache set predict,chip integration,chip IR drop,chip supply noise,circuit design methodology,clock distribution,clock grid,CMOS digital integrated circuits,design for reliability,design for test,digital circuits,high-frequency CMOS design,microprocessor test,microprocessors,power efficiency,RAIM,RAS,reliability,SRAM,system z,VLSI design,zEnterprise,zEnterprise 196,z196,45 nm SOI

AI Read Science

Must-Reading Tree

Example

Generate MRT to find the research sequence of this paper

Chat Paper

Summary is being generated by the instructions you defined