A 0.7-V 26.2-28.5 GHz Dual-Loop Double-Sampling PLL with Floating Capacitor OTA Based Gm-CP Achieving a 45.4-Fsrms Jitter

Jun Chang,Hongzhi Liang, Yixiao Luo, Zeyu Peng, Zhe Li,Yi Shen,Shubin Liu,Zhangming Zhu

2025 IEEE Custom Integrated Circuits Conference (CICC)（2025）

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Key words

Phase-locked Loop,Floating Capacitor,Analog-to-digital Converter,Cycling Performance,Current Ratio,mW Power,Phase Noise,Noise Contribution,Noise Performance,Performance Perspective,Calibration Technique,Loop Stability,Regular Supply,Optimal Bandwidth,Detector Gain,Flicker Noise,Passive Filter,Reference Clock,Low Mismatch

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