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Inductive GNN-Based Methodology for Accurate and Fast Average Power Estimation of Synthesized ASIC Designs from RTL Simulation Bypassing Gate-Level Simulation

M. B. Rakesh, Pabitra Das, K. R. Sai Pranav,Amit Acharyya

IEEE Transactions on Circuits and Systems I Regular Papers(2025)

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Key words
Graph neural network,ASIC,power estimation,machine learning in EDA,accuracy,fast,technology node
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