Novel Logic & SRAM Interconnect Design for Advanced Complementary FET (CFET) Based Technology Nodes
2024 IEEE International Electron Devices Meeting (IEDM)（2024）
Key words
Technology Node,Logic Design,Interconnect Design,Complementary FET,Parasite,Circuit Performance,3D Structure,Aspect Ratio,Nanosheets,Inverter,Power Line,Resistant Parasites,Parasitic Capacitance
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