2Nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications Geoffrey Yeap , S.S. Lin , H.L. Shang , H.C. Lin , Y.C. Peng , M. Wang , PW Wang , CP Lin , KF Yu , WY Lee , HK Chen , DW Lin , BR Yang , CC Yeh , CT Chan , JM Kuo , C-M Liu , TH Chiu , MC Wen , T.L. Lee , CY Chang , R. Chen , P-H Huang , C.S. Hou , YK Lin , FK Yang , J. Wang , S. Fung , Ryan Chen , C.H. Lee , TL Lee , W. Chang , DY Lee , CY Ting , T. Chang , HC Huang , HJ Lin , C. Tseng , CW Chang , KB Huang , YC Lu , C-H Chen , C.O. Chui , KW Chen , MH Tsai , CC Chen , N. Wu , HT Chiang , XM Chen , SH Sun , JT Tzeng , K. Wang , YC Peng , HJ Liao , T. Chen , YK Cheng , J. Chang , K. Hsieh , A. Cheng , G. Liu , A. Chen , HT Lin , KC Chiang , CW Tsai , H. Wang , W. Sheu , J. Yeh , YM Chen , CK Lin , J. Wu , M. Cao , LS Juang , F. Lai , Y. Ku , S.M. Jang , L.C. Lu 2024 IEEE International Electron Devices Meeting (IEDM)（2024）
Key words
Technology Platform, HPC Applications, Mass Production, Product Design, Reduction In Power, Test Chip, Energy-efficient Technologies
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