Nb Contacts for Thermally-Stable High-Performance Logic and Memory Peripheral Transistor

R. Sarkar,R. Ritzenthaler,J. Everaert,P. Eyben,K. Sankaran,C. Porret, P. Gupta,J. Ganguly,H. Arimura,J. Geypen,E. Capogreco, S. Roh,V. Machkaoutsan,L. PB. Lima, M-S. Kim,A. Spessot,N. Horiguchi

2024 IEEE International Electron Devices Meeting (IEDM)（2024）

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Key words

Logic Transistors,Contact Resistance,Resistant Parasites,Transmission Line Model,Transmission Electron Microscopy Images,Device Performance,Process Flow,Technology Node,Diborane,Schottky Barrier Height,Peripheral Circuits,Silicide,Thermal Budget,Gate Stack

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