An Event-Triggered Asynchronous Incremental NS-SAR ADC Featuring Sampling-Rate Reconfigurability with Power-Scalability and Enabling AFE-ADC Co-Design Approach
IEEE ACCESS（2024）
Key words
Event detection,Clocks,Finite impulse response filters,Switches,Logic,Analog-digital conversion,System-on-chip,Noise shaping,Detectors,Crosstalk,ADC,ASIC,asynchronous SAR,CMOS,event-triggered,finite-impulse-response (FIR) filter,incremental ADC,noise-shaping SAR,readout electronics,oversampling ratio (OSR)
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