A 16gb 18gb/s/pin GDDR6 DRAM with Per-Bit Trainable Single-Ended DFE and PLL-less Clocking
Young-Ju Kim,Hye-Jung Kwon,Su-Yeon Doo,Yoon-Joo Eom, Young-Sik Kim, M. Ahn,Yong-Hun Kim, Sang-Hoon Jung,Sung-Geun Do,Chang-Yong Lee,Jae-Sung Kim,Dong-Seok Kang,Kyung-Bae Park,Jung-Bum Shin, Jong-Ho Lee,Seung-Hoon Oh, Sang-Yong Lee, J. Yu,Ji-Suk Kwon,Ki-Hun Yu,Chul-Hee Jeon,Sang-Sun Kim,Min-Woo Won,Gun-hee Cho,Hyun-Soo Park,Hyung-Kyu Kim, Jeongwoo Lee, Seunghyun Cho,Keon-Woo Park,Jae-Koo Park, Yong Jae Lee, Yongjun Kim, Y. Seo,Beob-Rae Cho,Chang-Ho Shin,ChanYong Lee, Youngseok Lee,Yoon-Gue Song,Sam-Young Bang,Youn-Sik Park,Seouk-Kyu Choi,Byeong-Cheol Kim, G. Han,Seung-Jun Bae,Hyuk-Jun Kwon, J. Choi, Y. Sohn,Kwang-il Park,Seong-Jin Jang IEEE International Solid-State Circuits Conference（2018）
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