Improved Parasitic Capacitance-Predictively Aware DTCO: Enhanced Cell Efficiency with Manufacturability and Scalability for 4f$^{\text{2}}$ VCT-Based DRAM
IEEE TRANSACTIONS ON ELECTRON DEVICES（2024）
Key words
Random access memory,Capacitance,Computer architecture,Scalability,Microprocessors,Couplings,Transistors,Air gap,bitline (BL),BL capacitance (C-BL),design technology co-optimization (DTCO),dynamic random access memory (DRAM),manufacturability,parasitic extraction,performance, power, area, and cost (PPAC),read speed,scalability,vertical channel transistor (VCT)
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