A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM with Advanced I/O Circuitry for High-Speed and Low-Power Applications

Hyun-A Ahn,Yoo-Chang Sung,Yong-Hun Kim,Janghoo Kim,Kihan Kim,Dong-Hun Lee, Young-Gil Go, Jae-Woo Lee,Jae-Woo Jung,Yong-Hyun Kim, Ga-Ram Choi, Jun-Seo Park, Bo-Hyeon Lee,Jinhyeok Baek,Daesik Moon, Joo-Youn Lim,Daihyun Lim,Seung-Jun Bae,Tae-Young Oh

IEEE Journal of Solid-State Circuits（2024）

引用 0|浏览12

关键词

Calibration,Power demand,Transistors,SDRAM,Clocks,Circuits,Bandwidth,Clock,duty cycle adjustor (DCA),fourth-generation 10 nm,high speed,I/O,internal voltage controller (IVC),low power,LPDDR5x,offset calibration,pre-emphasis

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