11.2 A 3D Integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with Up to 40% Energy Reduction at Iso-Area Footprint

Tony F. Wu,Huichu Liu,H. Ekin Sumbul,Lita Yang, Dipti Baheti, Jeremy Coriell,William Koven, Anu Krishnan, Mohit Mittal,Matheus Trevisan Moreira, Max Waugaman, Laurent Ye,Edith Beigné

IEEE International Solid-State Circuits Conference（2024）

引用 4|浏览26

关键词

3D Integration,Neural Network,Energy Consumption,Energy Conservation,Form Factor,Energy Requirements,Noise Sources,Memory Capacity,Strict Requirements,Time Requirements,Third Dimension,Pose Estimation,High Bandwidth,Energy Budget,Local Memory,Uncompressed,Machine Learning Process,Multicast,Ample Space,Footprint Area

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