Trap Passivation for Reducing On-Resistance and Saturation Voltage in Wafer-Bonded InGaAs-Channel/GaN-Drain Vertical FETs
IEEE Transactions on Electron Devices（2024）
Key words
Apertures,Logic gates,Transistors,Indium gallium arsenide,Electron traps,Electrodes,Silicon,Aperture,BAVET,capacitance-voltage measurement,current aperture vertical electron transistor (CAVET),current-blocking layer,diode,drain resistance,field-effect transistor,field plate,fixed trap charge,frequency dispersion,GaN,gate-aperture overlap,heterogeneous integration,heterojunction,hydrogen passivation,InAlAs,InGaAs,InGaAs/InGaN,InGaN,interface state density,interface traps,ion implantation,junction gate,lattice mismatched,ON-resistance,p-gate,power electronics,saturation voltage,space-charge region,threshold voltage,trap charge concentration,trap states,vertical transistor,wafer bonded junction,wafer bonding
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