Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond
IEEE Transactions on Electron Devices（2024）
Key words
3-nm process node,6T static random access memory (6T-SRAM),hybrid integration,Si/SiGe super-lattice FinFET (SL-FinFET),vertically stacked gate-all-around nanosheet FET (GAA NSFET)
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