A 3nm CMOS FinFlex™ Platform Technology with Enhanced Power Efficiency and Performance for Mobile SoC and High Performance Computing Applications

Shien-Yang Wu,C. H. Chang,M. C. Chiang,C. Y. Lin,J. J. Liaw,J. Y. Cheng,J. Y. Yeh,H. F. Chen, S. Y. Chang, K. T. Lai,M. S. Liang,K. H. Pan,J. H. Chen,V. S. Chang, T. C. Luo,X. Wang, Y. S. Mor, C. I. Lin, S. H. Wang, M. Y. Hsieh,C. Y. Chen,B. F. Wu, C. J. Lin, C. S. Liang,C. P. Tsao, C. T. Li, C. H. Chen,C. H. Hsieh,H. H. Liu, P. N. Chen,C. C. Chen,R. Chen,Y. C. Yeo,C. O. Chui,W. Chang,T. L. Lee,K. B. Huang,H. J. Lin, K. W. Chen,M. H. Tsai,K. S. Chen, X. M. Chen,Y. K. Cheng,C. H. Wang, W. Shue,Y. Ku,S. M. Jang,M. Cao,L. C. Lu, T. S. Chang

2022 International Electron Devices Meeting (IEDM)（2022）

引用 28|浏览3

关键词

5G mobile radio,CMOS FinFlex platform technology,critical design flexibility,enhanced power efficiency,fastest time-to-manufacturability,fin configurations,FinFET technologies,high performance computing applications,HPC,logic density,mobile SoC,performance optimization,size 3.0 nm,standard cells

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