Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)（2022）
Key words
battery constraints,AR glasses,electromyography input prototype wristband,write energy,low-power write-assist techniques,domain-specific optimization,SRAM internal operation sequences,memory energy reduction,sequential memory access patterns,augmented reality SoCs,SRAM circuits,SRAM design,low-energy hand gesture detection,custom memory,cycle count,operating frequency,sequential access operation modes,read energy,7nm 1MB sequential SRAM,SRAM-SoC interfaces,size 7.0 nm,memory size 1.0 MByte
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