DVINO: A RISC-V Vector Processor Implemented in 65nm Technology
Guillem Cabo,Gerard Candon,Xavier Carril,Max Doblas,Marc Dominguez,Alberto Gonzalez,Cesar Hernandez,Victor Jimenez,Vatistas Kostalampros,Ruben Langarita,Neiel Leyva,Guillem Lopez-Paradis,Jonnatan Mendoza,Francesco Minervini,Julian Pavon,Cristobal Ramirez,Narcis Rodas,Enrico Reggiani,Mario Rodriguez,Carlos Rojas,Abraham Ruiz,Victor Soria,Alejandro Suanes,Ivan Vargas,Roger Figueras,Pau Fontova,Joan Marimon,Victor Montabes,Adrian Cristal,Carles Hernandez,Ricardo Martinez,Miquel Moreto,Francesc Moll,Oscar Palomar,Marco A. Ramirez,Antonio Rubio,Jordi Sacristan,Francesc Serra-Graells,Nehir Sonmez,Lluis Teres,Osman Unsal,Mateo Valero,Luis Villa PROCEEDINGS OF THE 37TH CONFERENCE ON DESIGN OF CIRCUITS AND INTEGRATED SYSTEMS (DCIS 2022)（2022）
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