BMC-Based Temperature-Aware SBST for Worst-Case Delay Fault Testing under High Temperature
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS（2022）
Key words
Delays,Circuit faults,Temperature distribution,Registers,Logic gates,Symbols,Manufacturing,Bounded model checking (BMC),software-based self-testing (SBST),temperature-aware testing,worst case delay faults
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