A 16gb 9.5gb/s/pin LPDDR5X SDRAM with Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
2022 IEEE International Solid- State Circuits Conference (ISSCC)（2022）
Key words
speed enhancement techniques,fourth generation 10nm DRAM fabrication technology,power-efficient LPDDR5X,sense amplifier,extended dynamic voltage,frequency scaling core,low-power data aligner,low-power schemes exploiting dynamic voltage-frequency scaling,offset-calibrated readout sense amplifiers,fourth generation 10nm DRAM process,mobile systems,augmented reality,low-power DRAM.LPDDR,memory density,high-speed enabling features,per-pin DFE training,calibration training,size 10.0 nm
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