Low-Latency BCH-CRC Decoder for 3D CT NAND Flash Memory Applications
2021 SILICON NANOELECTRONICS WORKSHOP (SNW)（2021）
Key words
BCH code,decoding throughput,low-latency BCH-CRC decoder,3D CT NAND flash memory applications,hard-decision values,energy-consuming sensing operations,soft-decision values,BCH decoding algorithm,CMOS process,cost reduction,BCH-CRC concatenated coding scheme,user data length,message sequence,error correction capacity,error correction capacity,size 65.0 nm,time 2.795 mus,memory size 512 Byte,word length 9 bit,word length 16 bit,bit rate 191 Mbit/s
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