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A 7-Nm Four-Core Mixed-Precision AI Chip with 26.2-TFLOPS Hybrid-FP8 Training, 104.9-TOPS INT4 Inference, and Workload-Aware Throttling

Sae Kyu Lee,Ankur Agrawal,Joel Silberman,Matthew Ziegler,Mingu Kang,Swagath Venkataramani,Nianzheng Cao,Bruce Fleischer,Michael Guillorn,Matthew Cohen,Silvia M. Mueller,Jinwook Oh,Martin Lutz,Jinwook Jung,Siyu Koswatta,Ching Zhou,Vidhi Zalani,Monodeep Kar,James Bonanno,Robert Casatuta,Chia-Yu Chen,Jungwook Choi,Howard Haynie,Alyssa Herbert,Radhika Jain,Kyu-Hyoun Kim,Yulong Li,Zhibin Ren,Scot Rider,Marcel Schaal,Kerstin Schelm,Michael R. Scheuermann,Xiao Sun,Hung Tran,Naigang Wang,Wei Wang,Xin Zhang,Vinay Shah,Brian Curran,Vijayalakshmi Srinivasan,Pong-Fei Lu,Sunil Shukla,Kailash Gopalakrishnan,Leland Chang

IEEE Journal of Solid-State Circuits（2021）

Cited 18|Views2
Key words
Training,Artificial intelligence,AI accelerators,Inference algorithms,Computer architecture,Bandwidth,System-on-chip,Approximate computing,artificial intelligence (AI),deep neural networks (DNNs),hardware accelerators,machine learning (ML),reduced precision computation
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