Heterogeneous Integration of BEOL Logic and Memory in a Commercial Foundry: Multi-Tier Complementary Carbon Nanotube Logic and Resistive RAM at a 130 Nm Node

T. Srimani,G. Hills,M. Bishop, C. Lau, P. Kanhaiya,R. Ho,A. Amer, M. Chao,A. Yu, A. Wright, A. Ratkovich, D. Aguilar, A. Bramer, C. Cecman, A. Chov, G. Clark, G. Michaelson, M. Johnson, K. Kelley, P. Manos, K. Mi, U. Suriono, S. Vuntangboon, H. Xue, J. Humes, S. Soares, B. Jones, S. Burack, Arvind,A. Chandrakasan, B. Ferguson, M. Nelson,M. M. Shulaker

2020 IEEE SYMPOSIUM ON VLSI TECHNOLOGY（2020）

Cited 24|Views37

Key words

monolithic 3D standard cell library,vertical interconnects,electronic design automation tools,silicon CMOS infrastructure,BEOL SRAM,RRAM memory,VLSI design infrastructure,resistive RAM,two-dimensional scaling,heterogeneous integration,carbon nanotube field-effect transistor logic technology,BEOL-compatible resistive RAM technology,BEOL nanoscale inter-layer vias,monolithic 3D process design kit,BEOL interconnect stack,monolithic 3D tiers,complementary CNFET logic,foundry technology,monolithic 3D integration,back-end-of-line integration,multitier complementary carbon nanotube logic,commercial foundry,BEOL logic,Si,word length 16 bit,size 130.0 nm

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