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Trap-Induced Data-Retention-Time Degradation of DRAM and Improvement Using Dual Work-Function Metal Gate

IEEE ELECTRON DEVICE LETTERS(2021)

Cited 8|Views8
Key words
Logic gates,Random access memory,Metals,Leakage currents,Green&apos,s function methods,Energy states,Electric fields,Data retention time,DRAM,gate-induced drain leakage (GIDL) current,trap-assisted tunneling (TAT),TCAD simulation,Green&#8217,s function method
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