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Bias-Dependent Variation in FinFET SRAM

IEEE Transactions on Very Large Scale Integration (VLSI) Systems(2020)

Cited 4|Views116
Key words
Random access memory,FinFETs,Hardware,Mathematical model,Voltage measurement,Logic gates,Drain-induced barrier lowering (DIBL),fin field effect transistor (FinFET),local layout effects (LLE),scaling,static noise margin (SNM),static random access memory (SRAM),statistics,variation,Vmin,write margin (WRM),yield
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