ETTORE: a 12-Channel Front-End ASIC for SDDs with Integrated JFET

Paolo Trigilio,Luca Bombelli,Marco Carminati,Riccardo Bisognin,Andrea Grande,Matteo Gugiatti,Carlo Fiorini,Peter Lechner,Tim Brunst,Susanne Mertens

2018 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE PROCEEDINGS (NSS/MIC)（2018）

Cited 9|Views9

Key words

ETTORE,front-end ASIC,SDDs,integrated JFET,front-end analog electronics,electron detector,TRISTAN Project,keV-scale sterile neutrinos,tritium β-decay,unprecedented accuracy,12-channel prototype ASIC,integrated nJFET,feedback loop,transistor,charge integration capacitor,detector chip,AC-coupled amplifier,15 μs exponential decay,external ADC,good pile-up rejection,high electron rates,output rise time,foreseen long tracks,detector JFET,0.35 μm AMS CMOS technology,measured performances,project requirements,time 15.0 mus,time 50.0 ns,capacitance 70.0 pF,size 0.35 mum,power 15.0 mW,time 40.0 ns,electron volt energy 127.0 eV

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