Interconnect Stack Using Self-Aligned Quad and Double Patterning for 10nm High Volume Manufacturing

A. Yeoh,A. Madhavan,N. Kybert, S. Anand,J. Shin,M. Asoro,S. Samarajeewa,J. Steigerwald, C. Ganpule,M. Buehler,A. Tripathi, V. Souw,M. Haran,S. Nigam,V. Chikarmane,P. Yashar,T. Mule, Y-H. Wu,K-S. Lee, M. Aykol, K. Marla,P. Sinha, S. Kirby,H. Hiramatsu, W. Han, M. Mori,M. Sharma, H. Jeedigunta,M. Sprinkle,C. Pelto, M. Tanniru,G. Leatherman,K. Fischer,I. Post,C. Auth

2018 IEEE International Interconnect Technology Conference (IITC)（2018）

Cited 34|Views14

Key words

high volume manufacturing,interconnect pitches,Intel high performance logic technology,interconnect stack,self-aligned quad,self-aligned double patterned layers,quad patterned interconnect layers,Moore law,contact-over-active-gate layout,cobalt metallization,pitch quartered interconnect layers,electromigration,gapfill-resistance requirements,size 10.0 nm,size 40.0 nm

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