14Nm FinFET Technology SRAM Cell Margin Evaluation and Analysis by Local Layout Effect

S. Y. Mun,D. Burnett,K. Y. Lim,S. Parihar, Y. J. Shi,H. C. Lo,W. Hong, K. J. Lee,O. Hu,J. Versaggi, C. Jerome, J. G. Lee,S. B. Samavedam,D. K. Sohn

IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference（2017）

Cited 2|Views24

Key words

Pass Gate,strap cell,SRAM NFET Vtsat,array edge degrading ADM,Gate-cut,ADM degradation,local layout effect,advanced Replacement Metal Gate module,planar CMOS technology,layout variety,tighter minimum design rule,high reaction energy diffuses,RMG,FinFET technology,PG Vtsat degrading ß-ratio,sensitive Access Disturb Margin response,fluorine,SRAM cell margin evaluation,size 14.0 nm

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