VIPRAM_L1CMS: A 2-Tier 3D Architecture for Pattern Recognition for Track Finding

J. R. Hoff,G.W. Deptuch,S. Joshi,T. Liu, J. Olsen,A. Shenai

2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD)（2016）

引用 3|浏览36

关键词

detector layers,VIPRAM_L1CMS,Pulsar2b Architecture,2-tier 3D architecture,HEP tracking trigger applications,individual detector hit,future LHC experiments,Level 1 Trigger system,high-speed track finding,high-speed readout architecture,VIPRAML1CMS,2-Tier Vertically Integrated chip,Level 1 trigger applications,15-bit wide detector addresses,complete pipelined Pattern Recognition Associative Memory architecture

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