BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-Nm FinFET.
2018 48TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC)（2018）
关键词
merged layout structure,SPICE model,BJT device modeling,circuit co-optimization,BJT variability,SoC-FPGA,thermal gradients,power density,FinFET CMOS technology,core components,critical analog blocks,temperature sensors,high-precision bandgap references,scaled process technologies,temperature sensing,bandgap reference circuit,test-chip device arrays,circuit application performance,circuit implementation,benchmark analog circuitry,size 7 nm
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