Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
International Symposium on Circuits and Systems（2018）
关键词
feedback loop,DFE,digital circuits,wireline RX,analog-to-digital converter,parallel digital equalizer implementation,digital equalizer datapath,inverse-DFT core,low-area VLSI implementation,parallel implementation technique,ultra-high-speed wireline receiver,high-speed wireline serial link receiver,inter-symbol interference,continuous-time linear equalizer,decision-feedback equalizer,ISI,discrete Fourier transform core,complex multipliers,convolution theorem
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