A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference.
2018 IEEE SYMPOSIUM ON VLSI CIRCUITS（2018）
关键词
AI trainina,multiTOPS AI core,deep learning training,edge devices,data centers,programmable architecture,custom ISA,neural network topologies,dataflow architecture,on-chip scratchpad hierarchy,aggressive inference performance,CMOS,binary integer,ternary integer,compute precision optimization,AI inference,scalable multiteraOPS deep learning processor core,TOPS binary peak performance,floating point,frequency 1.5 GHz,computer speed 1.5 TFLOPS,size 14.0 nm
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