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Design-synthesis Co-Optimisation Using Skewed and Tapered Gates.

Ayan Datta,James D. Warnock, Ankur Shukla,Saurabh Gupta, Yiu. H. Chan, Karthik Mohan,Charudhattan Nagarajan

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)(2016)

Cited 0|Views29
Key words
High Performance design,skewed gates,tapered gates,efficient timing closure,timing improvement,standard cell design,optimising synthesis
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