PMOSFET Layout Dependency with Embedded SiGe Source/Drain at POLY and STI Edge in 32/28nm CMOS Technology
VLSI Technology, Systems, and Applications（2012）
Key words
CMOS integrated circuits,Ge-Si alloys,MOSFET,CMOS technology,PMOSFET layout,POLY edge,STI edge,SiGe,SiGe source/drain,device performance,device variability,performance degradation
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