A 658kgates E-Streaming Video Decoder for Digital Home Applications

Chi-Cheng Ju,Kung-Sheng Lin,Tsu-Ming Liu, Chang,Chih-Ming Wang,Hue-Min Lin,Chia-Yun Cheng,Chun-Chia Chen,Fred Chiu,Chung-Bin Wu,Sling Liang,Sheng-Jen Wang, Ginny Chen, T. C. Hsiao,Joe Chen

2009 IEEE Asian Solid-State Circuits Conference（2009）

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关键词

SRAM chips,logic gates,variable length codes,video coding,RV VLD table reduction,RV temporal reference method,SRAM,digital home applications,e-streaming video decoder,logic gates,memory management,multi-stage pipeline,power 195 mW,size 55 nm

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