ETSOI CMOS for System-on-chip Applications Featuring 22nm Gate Length, Sub-100Nm Gate Pitch, and 0.08µm 2 SRAM Cell
Symposium on VLSI Technology（2011）
关键词
CMOS memory circuits,SRAM chips,low-power electronics,system-on-chip,SRAM cell,capacitance reduction,extremely thin SOI CMOS,gate length,gate pitch,low power electronics,multiVt transistors,size 22 nm,system-on-chip applications
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