A Sub-200 Fs Rms Jitter Capacitor Multiplier Loop Filter-Based Pll in 28 Nm Cmos for High-Speed Serial Communication Applications
2013 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC)（2013）
关键词
CMOS digital integrated circuits,active filters,capacitors,integrated circuit noise,jitter,mean square error methods,multiplying circuits,passive filters,phase locked loops,PLL performance,RMS jitter,analog PLL,capacitor multiplier loop filter-based PLL,capacitor multiplier-based active loop filter,current 15.5 mA,digital CMOS process,digital PLL,frequency 8 GHz to 12.2 GHz,high-speed serial communication applications,jitter performance,passive loop filter-based version,size 28 nm,voltage 1 V
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