Chip-level Power-Performance Optimization Through Thermally-Driven Across-Chip Variation (ACV) Reduction

X. Yu,O. Gluschenkov,N. D. Zamdmer, J. Deng,B. A. Goplen,H. S. Landis,L. R. Logan,J. A. Culp,Y. Liang,M. Cai, W. Lee,N. Rovedo,F. D. Tamweber, D. M. Lea,B. J. Greene,J. Sim,D. K. Slisher,A. I. Chou, P. Chang, H. Trombley,E. J. Nowak,S. V. Deshpande,W. K. Henson,A. C. Mocuta,K. Rim

International Electron Devices Meeting（2011）

Cited 4|Views2

Key words

MOSFET,annealing,elemental semiconductors,low-power electronics,silicon,silicon-on-insulator,MOSFET,SOI technology,Si,chip-level leakage quantitative,chip-level power-performance optimization,leakage power-performance trade-off,optimized thermal anneal process,size 32 nm,thermally-driven ACV reduction,thermally-driven across-chip variation reduction

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