Partially Depleted Silicon-On-Insulator (soi): A Device Design/Modeling and Circuit Perspective
ICM 2000 PROCEEDINGS OF THE 12TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS（2000）
关键词
CMOS integrated circuits,SPICE,SRAM chips,VLSI,circuit simulation,delays,hysteresis,integrated circuit modelling,integrated circuit noise,microprocessor chips,semiconductor device models,silicon-on-insulator,CMOS VLSI design,CMOS design,PD CMOS SOI technology,PD SOI circuits,SOI-specific device design modifications,SOI-specific process modifications,SPICE-like models,SRAMs,Si-SiO2,circuit perspective,circuit simulation,circuit strategies,circuit styles,compact device models,delay hysteresis,device design,device modeling,dynamic circuits,microprocessors,noise margin reduction,partially depleted CMOS SOI technology,partially depleted SOI,partially depleted silicon-on-insulator,static circuits
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