High Performance CMOS Devices on SOI for 90 Nm Technology Enhanced by RSD (raised Source/drain) and Thermal Cycle/spacer Engineering

H Park,W Rau-Sch,H Utomo,K Matsumoto,H Nii,S Kawanaka, S Fisher, SH Oh,J Snare,W Clark,AC Mocuta, J Holt,R Mo,T Sato,D Mocuta,BH Lee,O Dokumaci, P O'Neil, D Brown, J Suenaga, Y Li, L Brown,J Nakos, K Hathorn,P Ronsheim, H Kimura,B Doris,G Sudo, K Scheer,S Mittl, T Wagner, T Umebayashi, M Tsukamoto,Y Kohyama,J Cheek,I Yang, H Kuroda,Y Toyoshima,J Pellerin,D Schepis,P Agnello,J Welser

Washington, DC, USA（2003）

引用 11|浏览1

关键词

CMOS integrated circuits,MOSFET,nickel compounds,silicon-on-insulator,1.0 V,40 nm,5.4 ps,90 nm,MOL process,NFET,PFET,RSD engineering,S/D doping final spacer,Si-NiSi-SiO/sub 2/,disposable spacer,dopant deactivation,effective gate oxide thickness,gate activation,gate inversion,high performance CMOS devices,inverter delay,partially depleted SOI,post-activation thermal cycles,raised source/drain engineering,series resistance,silicide proximity,thermal cycle/spacer engineering,thermally optimized middle-of-line process

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