On the Retention Time Distribution of Dual-Channel Vertical DRAM Technologies

J Beintner,Y Li, D Casarotto,D Chidambarrao,K McStay,G Wang,K Hummler,R Divakaruni,W Bergner,E Crabbe,W Mueller,P Poechmueller,G Bronner

2003 International Symposium on VLSI Technology, Systems and Applications Proceedings of Technical Papers (IEEE Cat No03TH8672)

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关键词

DRAM chips,JFET integrated circuits,leakage currents,asymmetric vertical device design,buried strap outdiffusion,defect levels,dual channel vertical transistor DRAM technology,gated-diode measurements,high junction electric field,junction depletion volume,leakage current,p-well concentration,probe storage,retention time distribution,shallow arsenic bitline junction

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