A High Performance 90nm SOI Technology with 0.992 Μm/sup 2/ 6T-SRAM Cell
Digest International Electron Devices Meeting,
关键词
CMOS logic circuits,SRAM chips,cellular arrays,integrated circuit design,integrated circuit interconnections,integrated circuit metallisation,masks,nitridation,silicon-on-insulator,45 nm,6T-SRAM cell,90 nm,CMOS logic technology,SOI technology,Si,SiLK low-K dielectric material,backend of the line,cell area,damascene local interconnect,front-end of line,ground rules,hierarchical Cu metallization,multilayer hard mask stack,super-halo design concepts,ultra-thin heavily nitrided gate dielectric
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