A 36 Gbps 16.9 Mw/gbps Transceiver in 20-Nm CMOS with 1-Tap DFE and Quarter-Rate Clock Distribution

Takushi Hashida,Yasumoto Tomita,Yuuki Ogata,Kosuke Suzuki, Shigeto Suzuki,Takanori Nakao, Yuji Terao, Satofumi Honda,Sota Sakabayashi,Ryuichi Nishiyama,Akihiko Konmoto,Yoshitomo Ozeki,Hiroyuki Adachi,Hisakatsu Yamaguchi,Yoichi Koyanagi,Hirotaka Tamura

2014 Symposium on VLSI Circuits Digest of Technical Papers（2014）

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Key words

CMOS analogue integrated circuits,MMIC frequency convertors,clock distribution networks,decision feedback equalisers,delay lock loops,field effect MMIC,frequency multipliers,radio transceivers,1-tap DFE,bit rate 36 Gbit/s,clock-delivery power,continuous-time linear equalizer,delay-locked loop,frequency 9 GHz,frequency doublers,jitter,multiphase half-rate clock signals,power 609.9 mW,quarter-rate clock distribution,size 20 nm,skew,transceiver front-ends,voltage 0.9 V

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