A Universal FPGA-based Floating-Point Matrix Processor for Mobile Systems
PROCEEDINGS OF THE 2014 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT)（2014）
Key words
field programmable gate arrays,floating point arithmetic,matrix algebra,ARM cortex A9,DE3 develop board,GFLOPS,NIOS II/f soft-core processor,desktop processor,energy efficiency,field programmmable gate array,hardware-software interface,master processor,matrix accelerator,matrix cache,mobile system,multiple matrix-matrix operation,on-chip communication,universal FPGA-based floating-point matrix processor
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