A 40 Nm CMOS 195 Mw/55 Mw Dual-Path Receiver AFE for Multi-Standard 8.5–11.5 Gb/s Serial Links
IEEE Journal of Solid-State Circuits（2014）
关键词
ADC bit error rate,backplane,dual-path,multimode fiber,offset calibration,rectifying error correction,rectifying flash ADC,serial link,10GBase,timing-interleaving ADC
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