A 32 Gb/s Data-Interpolator Receiver with Two-Tap DFE Fabricated with 28-Nm CMOS Process.
IEEE Journal of Solid-State Circuits（2013）
Key words
Clock and data recovery,data interpolator,decision feedback equalizer
AI Read Science
Must-Reading Tree
Example
Generate MRT to find the research sequence of this paper
Chat Paper
Summary is being generated by the instructions you defined