Da-Wen Lin - Taiwan Semicond Mfg Co | 人才画像

基本信息

Career Trajectory

Bio

Da-Wen Lin received the B.S. and M.S. degrees in electronics engineering from the National Chiao Tung University, Hsinchu, Taiwan, in 1996 and 1998, respectively, where he is currently working toward the Ph.D. degree at the Institute of Electronics Engineering. In 2000, he joined Taiwan Semiconductor Manufacturing Company, Hsinchu. His work mainly focuses on the ultra-shallow-junction design and strain engineering for mobility enhancement of advanced logic CMOS devices. He is currently working on 22 nm node CMOS device technology research and development. He is the holder of five U.S. patents as well as six Taiwanese patents in the field of CMOS fabrication. His research interests include the extraction of MOSFET series resistance and carrier mobility enhancement with strained silicon. Mr. Lin is a member of the Phi Tau Phi.

Research Interests

Papers共 33 篇Author StatisticsCo-AuthorSimilar Experts

By YearBy Citation主题筛选期刊级别筛选合作者筛选合作机构筛选

2Nm Platform Technology Featuring Energy-Efficient Nanosheet Transistors and Interconnects Co-Optimized with 3DIC for AI, HPC and Mobile SoC Applications

Geoffrey Yeap,S.S. Lin, H.L. Shang, H.C. Lin, Y.C. Peng, M. Wang,PW Wang, CP Lin,KF Yu, WY Lee,HK Chen,DW Lin,BR Yang,CC Yeh, CT Chan, JM Kuo, C-M Liu, TH Chiu, MC Wen,T.L. Lee, CY Chang, R. Chen, P-H Huang,C.S. Hou, YK Lin, FK Yang, J. Wang, S. Fung, Ryan Chen, C.H. Lee,TL Lee, W. Chang, DY Lee, CY Ting, T. Chang, HC Huang,HJ Lin, C. Tseng, CW Chang,KB Huang,YC Lu, C-H Chen,C.O. Chui, KW Chen,MH Tsai, CC Chen, N. Wu,HT Chiang, XM Chen,SH Sun,JT Tzeng, K. Wang, YC Peng, HJ Liao, T. Chen,YK Cheng, J. Chang, K. Hsieh, A. Cheng, G. Liu, A. Chen,HT Lin, KC Chiang, CW Tsai, H. Wang, W. Sheu, J. Yeh, YM Chen, CK Lin, J. Wu, M. Cao, LS Juang, F. Lai, Y. Ku,S.M. Jang, L.C. Lu

2024 IEEE International Electron Devices Meeting (IEDM)pp.1-4, (2024)

Cited0Views0EIWOSBibtex

5Nm CMOS Production Technology Platform Featuring Full-Fledged EUV, and High Mobility Channel FinFETs with Densest 0.021µm2 SRAM Cells for Mobile SoC and High Performance Computing Applications

Geoffrey Yeap,S. S. Lin, Y. M. Chen, H. L. Shang,P. W. Wang, H. C. Lin,Y. C. Peng,J. Y. Sheu,M. Wang,X. Chen,B. R. Yang, C. P. Lin, F. C. Yang,Y. K. Leung,D. W. Lin, C. P. Chen,K. F. Yu,D. H. Chen, C. Y. Chang,H. K. Chen, P. Hung,C. S. Hou,Y. K. Cheng,J. Chang, L. Yuan,C. K. Lin,C. C. Chen,Y. C. Yeo,M. H. Tsai,H. T. Lin,C. O. Chui,K. B. Huang,W. Chang,H. J. Lin, K. W. Chen,R. Chen,S. H. Sun, Q. Fu, H. T. Yang,H. T. Chiang,C. C. Yeh,T. L. Lee,C. H. Wang,S. L. Shue, C. W. Wu,R. Lu,W. R. Lin,J. Wu, F. Lai, Y. H. Wu, B. Z. Tien,Y. C. Huang, L. C. Lu,Jun He, Y. Ku,J. Lin,M. Cao, T. S. Chang,S. M. Jang

2019 IEEE International Electron Devices Meeting (IEDM) (2019)

Cited159Views0EIWOSBibtex

159

Integrated circuit resistor

Kingyuen Wong,Chiapin Lin,Chiayu Lu, Yicheng Tsai,Dawen Lin,Kuofeng Yu

mag（2014）

Cited23Views0Bibtex

Transistor having notched fin structure and method of making the same

Chihhung Tseng,Dawen Lin,Chientai Chan,Chiapin Lin, Liwen Weng, Anshen Chang, W U Chungcheng

mag（2014）

Cited42Views0Bibtex

METHODS OF ANNEALING AFTER DEPOSITION OF GATE LAYERS

Chun Hsiung Tsai, Y U Xiongfei,Yulien Huang,Dawen Lin

mag（2014）

Cited23Views0Bibtex

Rapid thermal annealing to reduce pattern effect

Chun Hsiung Tsai,W U Chiiming,Dawen Lin

mag（2014）

Cited23Views0Bibtex

Asymmetric rapid thermal annealing to reduce pattern effect

Chun Hsiung Tsai,W U Chiiming,Dawen Lin

mag（2013）

Cited25Views0Bibtex

Device with Engineered Epitaxial Region and Methods of Making Same

Kingyuen Wong,Chiayu Lu,Chienchang Su, Yenchun Lin,Yifang Pai,Dawen Lin

mag（2013）

Cited23Views0Bibtex

High surface dopant concentration semiconductor device and method of fabricating

Yulien Huang,Maorong Yeh,Chun Hsiung Tsai, Tsunghung Lee,Dawen Lin,Tszmei Kwok

mag（2012）

Cited36Views0Bibtex

Multi-threshold voltage device and method of making same

Chungyu Chiang,Dawen Lin,Shyhwei Wang

mag（2012）

Cited26Views0Bibtex

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